It is fun to occasionally build circuits using discrete semiconductors rather than with ICs. A 5000 Hz digital clock was needed for an experiment. It was decided to use multivibrators for the basic oscillator and a divide by 2.
Figure 5 is the entire circuit. The tuning range of the astable multivibrator was about 7060-10650 Hz. The 5K pot was slowly adjusted until 10000 Hz was measured in a frequency counter. Following testing of the astable multivibrator, the flip flop was built and examined. Astable multivibrator function has been discussed previously on this web site.
Please refer to the bistable multivibrator. It is a one input circuit set up for toggle or flip-flop operation. Negative edge pulses applied between the two 0.001 capacitors will cause the binary state of Q1 and Q2 to change to the opposite state. The multivibrator circuit is made up of Q1, Q2 and the 47K and 1K base and collector resistors respectively. The other components D1, D2, the RS resistors and CS capacitors comprise a steering circuit to generate the proper response to the negative edge pulses. When a negative input pulse arrives, it is guided to the base terminal of the ON transistor, but prevented from reaching the base terminal of the OFF transistor.
In order to study this circuit at DC, I temporarily exchanged the 0.001 timing capacitors in the astable multivibrator with some 22 uF electrolytic caps to slow it down. Referring back to the bistable multivibrator, let us assume that Q1 is OFF and Q2 is ON. The collector voltage of Q1 is high (cut off). The collector voltage of Q2 is low (saturation). The Q1 collector is connected to the cathode of D1 by the 100K RS resistor. The cathode of D1 is reverse biased by the high Q1 collector voltage and also because its anode is held close to 0 volts by the 47K resistor connected to the collector terminal of Q2. It would take a very strong negative input pulse to forward bias D1 enough to reach the Q1 base terminal. The Q2 collector voltage is nearly 0 volts and therefore the D2 cathode has little to no reverse bias voltage via its RS. Thus, any small amplitude negative input pulse will cause D2 to become forward biased, reach the base of Q2 and drive Q2 OFF. Once Q2 switches off, in turn Q1 is toggled ON and its collector voltage goes low. The large reverse bias on D1 disappears. However, Q2 is now OFF and D2 will now be strongly reverse biased which will steer the next negative input pulse to the base of Q1. This is the basis of the circuit's negative edge flip-flop operation.
In another experiment, I changed the .001 C0G capacitors of the astable multivibrator to 470 pF. This gave a usable range of 22968 to 14832 Hertz (11484-7416 Hz at the Q1 and Q2 output) . Looking at the output of the flip-flop in the oscilloscope; at the higher frequency range, the flip-flop could not keep up and failed to divide by 2. I found experimentally that the time constant of each of the CS and RS components seemed to be the problem. When the CS capacitors were also decreased to 470 pF, the flip-flop worked properly.
As you increase the flip-flop operation frequency, speed up bypass capacitors might also be required across the 47K base resistors of Q1 and Q2 . A suggested starting value to try is 220 pF. Some builders also bypass the resistors in the RS steering circuit at higher frequencies, however, this is getting a little crazy. It is really important to look at the output waveform in the oscilloscope to ensure reasonable performance.
Shown above is the Figure 5 breadboard prototype.
5 KHz output waveform of Q2
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